Modern electronic products tend to be light, slim, and small, and, such products usually exhibit high performance, multi-functionality, and high efficiency. Such design characteristics are often made possible by using flip chip semiconductor package technology, an advanced semiconductor packaging technology. In the current technology, a plurality of electrode pads is deposited on the surface of a semiconductor integrated circuit (IC) chip. Additionally, solder bumps are formed on the electrode pads, and electrically connecting pads corresponding to the solder bumps are formed on an organic electronic package substrate, providing a package wherein the chip is installed on the package substrate facing down on the conductive surface.
Since more and more products are designed with the goal of miniaturization, applications for flip chip technology are continuously expanding, making it a standard chip package technology. Meanwhile, passive components such as electrical resistors, capacitors and inductors are typically needed within devices to improve the electrical performance. Such passive components are adhered to a circuit board using surface mount technology, such that solder bumps and a surface adherent metal element co-exist on the circuit board. These solder materials and components with different heights and sizes are mixed together with a semiconductor chip of a different type to be electrically conducted.
Currently, stencil-printing technology is popularly used to form a solder material on a substrate. Referring to FIG. 1, the current stencil-printing technology mainly provides a substrate 10, a plurality of electrically connecting pads 12 on the substrate 10, and a solder mask 11 printed on the surface of the substrate 10, the solder mask 11 having openings to expose the electrically connecting pads 12. During application of the solder material, a stencil 13 with a plurality of grids 13a is placed on the substrate 10. After coating the stencil 13 with the solder material, a scraper 14 scrapes the stencil 13 or a spraying process is performed, such that the grids 13a of the stencil 13 are filled with the solder material. Additionally, a solder layer (not shown) is formed on the electrically connecting pads after removing the stencil 13. Subsequently, under a reflow-soldering process at a temperature at which solder melts, the solder is reflowed to form a solder element (not shown) on the electrically connecting pads 12 of the substrate 10, such that the solder element provides for external electrical connection. Therefore, solder is formed with different heights and sizes by electroplating on the electrically connecting pads of the substrate during different electroplating processes. Furthermore, an electrically connecting contact is formed with different heights to electrically connect semiconductor chips that are adhered on different surfaces.
However, a portion of the electrically connecting pads is covered by an insulating protective layer covering the electrically connecting pads, which causes the size of the exposed electrically connecting pads to be smaller. In addition, This lack of exposure causes a problem in allocating the subsequent solder material, causing the solder to be poorly adhered on the electrically connecting pads, resulting in low yield of such stencil printing technology. In particular, a circuit board with high circuit density experiences significant difficulty in terms of allocation and adhesion.
To address the problems involving solder material for stencil printing, electroplating technology has been used to form solder material on circuit boards, wherein the requirement of providing thin circuits is still satisfied. Referring to Taiwan Patent No. 508987 entitled “Method for Solder Electroplating,” FIGS. 2A to 2F, demonstrate a circuit board 20 with an electrically connecting pads 201 that is covered with an organic insulating protective layer (solder mask) 21. First, referring to FIG. 2A, a plurality of openings 211 is formed in the protective layer 21 by a patterning process to expose the electrically connecting pads 201. Referring to FIG. 2B, a conductive layer 22 is formed on the surface of the protective layer 21 by physical vapor deposition. Then, referring to FIG. 2C, a resist layer 23 is formed over the surface of the conductive layer 22, and openings 231 are formed in the resist layer to expose the electrically connecting pads 201. Subsequently, referring to FIG. 2D, a solder material 24 is formed in the openings 231 by an electroplating process using the conductive layer 22 as a conductive path. Additionally, referring to FIG. 2E, the resist layer 23 and the conductive layer 22 covered by the resist layer are removed. Finally, referring to FIG. 2F, pre-solder bumps 24′ are formed by a reflow-soldering process.
Furthermore, a similar solder material is often chosen for forming pre-solder bumps or the solder material on each of the electrically connecting pads of a circuit board by either stencil printing or electroplating, such that the pre-solder bumps and the solder material have the same conductivity. However, a better conductive material is sometimes needed when conductivity is critical or optimal mechanical connections are required. Therefore, it is not always ideal to use similar materials for various features.
Moreover, the bumps for electrically connecting a chip that are formed on the electrically connecting pads of the circuit board and the solder balls that electrically connect to the printed circuit board (PCB) are electrically connected to different electronic devices. Therefore, the materials for the bumps and the solder balls are different, requiring formation of structures with two different materials by electroplating on the circuit board. A resist layer must be formed on the circuit board, and an opening is formed on the resist layer to expose a portion of the electrically connecting pads, such that the bumps can be formed by electroplating on the electrically connecting pads. Then, the resist layer is removed, and another resist layer is formed. Additionally, the bumps are covered by the new resist layer to expose the foregoing unexposed electrically connecting pads. Finally, solder balls are formed by electroplating on the subsequently exposed electrically connecting pads.
The bumps and solder balls having different materials formed on the circuit by electroplating require coverage with resist layers two different times, as well as the electroplating process and resist layer removal. Accordingly, fabrication complexity is increased, reducing productivity.
Additionally, the package thickness is increased by the electroplating used in formation of the bumps and/or the solder balls, and may result in uneven heights during the later electroplating process. However, it the bumps or the solder balls have uneven heights after reflow soldering, the electrical conductivity with the chip or printed circuit board can be reduced.
Therefore, it is desirable to create a design that overcomes the foregoing problems in achieving optimal mechanical and electrical connectivity.